The present invention relates to digital-to-analogue converters and digital-to-analogue converters incorporating a filtering function and is particularly (though not exclusively) concerned with their implementation using switched-capacitor techniques.
A typical, conventional arrangement is shown in FIG. 1, where successive sample values of a w-bit digital word [b.sub.o b.sub.l. . . b.sub.i. . . b.sub.w-1 ] are supplied to a digital-to-analogue converter (DAC) 1 followed by an analogue FIR (finite impulse response) filter 2, based on a conventional tapped delay line structure with delays z.sup.-1, filter coefficient multipliers h.sub.o. . . h.sub.N-1 and an adder (or of course a parallel structure may be used). The coefficients are selected to give any desired filter response; in general this will be a baseband response from DC to half the sampling frequency F.sub.s, followed by some rejection of unwanted frequencies above F.sub.s /2.
The DAC may employ switched capacitor techniques (as described for example in Roubik Gregorian--"High Resolution Switched Capacitor D/A Converter" --Microelectronics Journal, Vol. 12, No. 2, 1981 Mackintosh Publ. Ltd.); in the filter, the analogue delays may also be realised by switched-capacitor elements. The realisation of the analogue delays may however not be ideal.